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author | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
commit | c80315cea42414216bcc7b62acb2ef9a41b54eab (patch) | |
tree | bc089997bff5a8d906fc652441fdff803add06dd /passes | |
parent | fefb652d568749731b581185e6cb201f0fff479e (diff) | |
download | yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.gz yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.bz2 yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.zip |
Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 524d57854..c680dbbd8 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -625,16 +625,15 @@ struct HierarchyPass : public Pass { for (auto module : design->modules()) for (auto cell : module->cells()) { - if (GetSize(cell->parameters) != 0) - continue; - Module *m = design->module(cell->type); if (m == nullptr) continue; - if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) { - IdString new_m_name = m->derive(design, cell->parameters); + if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) { + IdString new_m_name = m->derive(design, cell->parameters, true); + if (new_m_name.empty()) + continue; if (new_m_name != m->name) { m = design->module(new_m_name); blackbox_derivatives.insert(m); |