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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:50:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:50:55 -0800 |
| commit | d152fe961ffb3d7ed0493cde5c21f88fe78644e1 (patch) | |
| tree | 9e4ece77a15793a0abb9194883140f731b3272cb /passes | |
| parent | 275e937fc16635edfd38c18ea9eb9f7cbbdd32c9 (diff) | |
| download | yosys-d152fe961ffb3d7ed0493cde5c21f88fe78644e1.tar.gz yosys-d152fe961ffb3d7ed0493cde5c21f88fe78644e1.tar.bz2 yosys-d152fe961ffb3d7ed0493cde5c21f88fe78644e1.zip | |
Fixes
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 1806b2d53..3c781ca44 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -413,11 +413,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip dict<IdString, bool> abc9_box; vector<RTLIL::Cell*> boxes; - for (auto cell : module->cells()) { + for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { + auto cell = it->second; if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) { - module->remove(cell); + it = module->cells_.erase(it); continue; } + ++it; RTLIL::Module* box_module = design->module(cell->type); auto jt = abc9_box.find(cell->type); if (jt == abc9_box.end()) @@ -996,7 +998,7 @@ struct Abc9Pass : public Pass { log_assert(!module->attributes.count(ID(abc9_box_id))); if (!design->selected_whole_module(module)) - log_cmd_error("Can't handle partially selected module %s!\n", log_id(module)); + log_error("Can't handle partially selected module %s!\n", log_id(module)); assign_map.set(module); |