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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-21 15:00:54 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-21 15:00:54 +0200 |
commit | dc07ae96774c649d23ea787e07d618670c7e93bf (patch) | |
tree | 04169026a40d40ca620dfa1ffc0ae6a4c04f7e8c /passes | |
parent | 57af8499dfc3c35d7327107ad30c1124c646fefd (diff) | |
download | yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.tar.gz yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.tar.bz2 yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.zip |
techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/techmap.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f98d1564a..8e6630c89 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -643,6 +643,8 @@ struct TechmapWorker if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0) + parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name)); for (auto &conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { @@ -1111,6 +1113,10 @@ struct TechmapPass : public Pass { log(" When a parameter with this name exists, it will be set to the type name\n"); log(" of the cell that matches the module.\n"); log("\n"); + log(" _TECHMAP_CELLNAME_\n"); + log(" When a parameter with this name exists, it will be set to the name\n"); + log(" of the cell that matches the module.\n"); + log("\n"); log(" _TECHMAP_CONSTMSK_<port-name>_\n"); log(" _TECHMAP_CONSTVAL_<port-name>_\n"); log(" When this pair of parameters is available in a module for a port, then\n"); |