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author | Clifford Wolf <clifford@clifford.at> | 2019-04-08 21:14:05 +0200 |
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committer | GitHub <noreply@github.com> | 2019-04-08 21:14:05 +0200 |
commit | e194e65358058f3a039636d2603cc093f7b75e50 (patch) | |
tree | 7a733f932cef75c1073a41d52618954acc69b9a7 /passes | |
parent | dfb242c905ff10bb4038f080aeb74a820e8fbd00 (diff) | |
parent | 2bf3ca64435b11726d87cc0d34e887a79351ec45 (diff) | |
download | yosys-e194e65358058f3a039636d2603cc093f7b75e50.tar.gz yosys-e194e65358058f3a039636d2603cc093f7b75e50.tar.bz2 yosys-e194e65358058f3a039636d2603cc093f7b75e50.zip |
Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
Diffstat (limited to 'passes')
-rw-r--r-- | passes/memory/memory_bram.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 804aa21f9..ddc56d9b5 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -744,7 +744,8 @@ grow_read_ports:; if (clken) { clock_domains[pi.clocks] = clkdom; clock_polarities[pi.clkpol] = clkdom.second; - read_transp[pi.transp] = transp; + if (!pi.make_transp) + read_transp[pi.transp] = transp; pi.sig_clock = clkdom.first; pi.sig_en = rd_en[cell_port_i]; pi.effective_clkpol = clkdom.second; |