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author | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:23:55 -0600 |
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committer | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:23:55 -0600 |
commit | 1fc061d90c45166f87d92f76b6fae1ec517be72f (patch) | |
tree | b7c0418b904bfe2e730d6a29cadabdcfcf416496 /techlibs/achronix/synth_speedster.cc | |
parent | adf17547290b403e863ed7c71960a5678c6bbfaf (diff) | |
download | yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.tar.gz yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.tar.bz2 yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.zip |
Organizing Speedster file names
Diffstat (limited to 'techlibs/achronix/synth_speedster.cc')
-rwxr-xr-x | techlibs/achronix/synth_speedster.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_speedster.cc index 8158c56fd..3808af6f1 100755 --- a/techlibs/achronix/synth_speedster.cc +++ b/techlibs/achronix/synth_speedster.cc @@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass { { if (check_label("begin")) { - run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v"); + run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); } @@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); - run("techmap -map +/achronix/speedster22i/cells_map_speedster.v"); + run("techmap -map +/achronix/speedster22i/cells_map.v"); run("dffinit -ff dffeas Q INIT"); run("clean -purge"); } |