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| author | Robert Ou <rqou@robertou.com> | 2017-08-01 11:58:01 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 12:13:25 -0700 |
| commit | 1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57 (patch) | |
| tree | 7180ae460b5518a73025fb8ecb7a8b8a0b0d6394 /techlibs/altera_intel/max10 | |
| parent | 007f29b9c221ab1a8931de863517d6990218970d (diff) | |
| download | yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.tar.gz yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.tar.bz2 yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.zip | |
coolrunner2: Add FFs with clock enable to cells_sim.v
Diffstat (limited to 'techlibs/altera_intel/max10')
0 files changed, 0 insertions, 0 deletions