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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-05 16:33:24 -0700 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:39 -0700 |
| commit | fe3a932cfa17c835f5e400c8fc8411635ba0c997 (patch) | |
| tree | 629abfe41e260818097fbd5276fb4ed84ccfd9ec /techlibs/altera_intel/synth_intel.cc | |
| parent | 007f29b9c221ab1a8931de863517d6990218970d (diff) | |
| download | yosys-fe3a932cfa17c835f5e400c8fc8411635ba0c997.tar.gz yosys-fe3a932cfa17c835f5e400c8fc8411635ba0c997.tar.bz2 yosys-fe3a932cfa17c835f5e400c8fc8411635ba0c997.zip | |
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
Diffstat (limited to 'techlibs/altera_intel/synth_intel.cc')
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