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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:08:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:08:04 -0800 |
| commit | 1a260ce89b79f0d4c2092f725b48583bd5e7bc41 (patch) | |
| tree | bef82baea6124458d7acc43bddbcfa990ee81876 /techlibs/anlogic/Makefile.inc | |
| parent | 2d98db73e39f17865ae26cdd00cf7c112521649f (diff) | |
| parent | 43030db5fff285de85096aaf5578b0548659f6b7 (diff) | |
| download | yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.tar.gz yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.tar.bz2 yosys-1a260ce89b79f0d4c2092f725b48583bd5e7bc41.zip | |
Merge pull request #712 from mmicko/anlogic-support
Initial support for Anlogic FPGA
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc new file mode 100644 index 000000000..750dced31 --- /dev/null +++ b/techlibs/anlogic/Makefile.inc @@ -0,0 +1,8 @@ + +OBJS += techlibs/anlogic/synth_anlogic.o +OBJS += techlibs/anlogic/anlogic_eqn.o + +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) |