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| author | whitequark <whitequark@whitequark.org> | 2020-01-02 21:06:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-02 21:06:17 +0000 |
| commit | f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (patch) | |
| tree | e7c5b19ffae2bfc40e682f696d2ae40513717ad7 /techlibs/anlogic/Makefile.inc | |
| parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
| parent | 550310e2647c7aac1e49b79d9ff912436103062f (diff) | |
| download | yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.gz yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.bz2 yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.zip | |
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 9426b5ca5..2d8d65e2e 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh)) |