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| author | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
| commit | 83b2e0272333cfcc2529e0833723a52c066146a6 (patch) | |
| tree | 9985b7f840383419ebd5b189023ca6871a02d5a9 /techlibs/anlogic/anlogic_determine_init.cc | |
| parent | b8cd4ad64ae9a45faecffc1a6b92a8219755bc60 (diff) | |
| parent | fb568ddb4e2ccaab352d9d062f6b4926aca75680 (diff) | |
| download | yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.gz yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.bz2 yosys-83b2e0272333cfcc2529e0833723a52c066146a6.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/anlogic/anlogic_determine_init.cc')
| -rw-r--r-- | techlibs/anlogic/anlogic_determine_init.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc index 34b1d4f8a..c4089dac2 100644 --- a/techlibs/anlogic/anlogic_determine_init.cc +++ b/techlibs/anlogic/anlogic_determine_init.cc @@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass { } } } - log_header(design, "Updated %lu cells with determined init value.\n", cnt); + log_header(design, "Updated %d cells with determined init value.\n", cnt); } } AnlogicDetermineInitPass; |