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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-07-31 11:49:48 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-01 17:27:34 +0200 |
| commit | 28b7053a01630def454e683f03953c74744da025 (patch) | |
| tree | d4e488538478a2adb4348e97c541775e0ec35a17 /techlibs/anlogic/anlogic_eqn.cc | |
| parent | b4f38cca77a78884ce215190935af78cae92c4db (diff) | |
| download | yosys-28b7053a01630def454e683f03953c74744da025.tar.gz yosys-28b7053a01630def454e683f03953c74744da025.tar.bz2 yosys-28b7053a01630def454e683f03953c74744da025.zip | |
Fix formatting for msys2 mingw build using GetSize
Diffstat (limited to 'techlibs/anlogic/anlogic_eqn.cc')
| -rw-r--r-- | techlibs/anlogic/anlogic_eqn.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index 741bf04cc..070d39a20 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass { } } } - log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt); + log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; |