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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-07-31 11:49:48 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-02 16:55:14 +0200 |
| commit | e9c5f1b3467d4566978dfb07c3b1fa91e94ef761 (patch) | |
| tree | 5abff1a829d11bcb317979b2525e0bf324ddb70e /techlibs/anlogic/anlogic_eqn.cc | |
| parent | 82a29720684dc8db452289321340bf6e78dcbd2c (diff) | |
| download | yosys-e9c5f1b3467d4566978dfb07c3b1fa91e94ef761.tar.gz yosys-e9c5f1b3467d4566978dfb07c3b1fa91e94ef761.tar.bz2 yosys-e9c5f1b3467d4566978dfb07c3b1fa91e94ef761.zip | |
Fix formatting for msys2 mingw build using GetSize
Diffstat (limited to 'techlibs/anlogic/anlogic_eqn.cc')
| -rw-r--r-- | techlibs/anlogic/anlogic_eqn.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index 741bf04cc..070d39a20 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass { } } } - log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt); + log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; |