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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-02 16:37:57 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-02 16:37:57 +0200 |
| commit | f4ae6afc2282bcefac51b65e3905293cb19adc72 (patch) | |
| tree | 2fef377b1811ef8030c4dbfdf5cabcada755cdd4 /techlibs/anlogic/anlogic_eqn.cc | |
| parent | e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf (diff) | |
| parent | 7a65ed19a5921ff219fd208d2712e09b5e5894dd (diff) | |
| download | yosys-f4ae6afc2282bcefac51b65e3905293cb19adc72.tar.gz yosys-f4ae6afc2282bcefac51b65e3905293cb19adc72.tar.bz2 yosys-f4ae6afc2282bcefac51b65e3905293cb19adc72.zip | |
Merge pull request #1239 from mmicko/mingw_fix
Fix formatting for msys2 mingw build
Diffstat (limited to 'techlibs/anlogic/anlogic_eqn.cc')
| -rw-r--r-- | techlibs/anlogic/anlogic_eqn.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index 741bf04cc..070d39a20 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass { } } } - log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt); + log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; |