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| author | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-21 11:32:44 -0700 |
|---|---|---|
| committer | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-21 11:32:44 -0700 |
| commit | f8b97e21f3f76dd031f82586f8af104368f03e73 (patch) | |
| tree | bce4710ca14bfc263c3677034fc630bed64fe2ac /techlibs/anlogic/anlogic_eqn.cc | |
| parent | 7b964bfb83696ac66f31e560d8c0c475da2b5c10 (diff) | |
| download | yosys-f8b97e21f3f76dd031f82586f8af104368f03e73.tar.gz yosys-f8b97e21f3f76dd031f82586f8af104368f03e73.tar.bz2 yosys-f8b97e21f3f76dd031f82586f8af104368f03e73.zip | |
using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal
Diffstat (limited to 'techlibs/anlogic/anlogic_eqn.cc')
0 files changed, 0 insertions, 0 deletions