diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
| commit | 24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch) | |
| tree | 131c64cee5a0cf09adc68b32f25e06a9da668ad0 /techlibs/anlogic/arith_map.v | |
| parent | 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff) | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.gz yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.bz2 yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.zip | |
Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'techlibs/anlogic/arith_map.v')
| -rw-r--r-- | techlibs/anlogic/arith_map.v | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index 11cd140ec..6d6a7ca37 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -42,10 +42,9 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; + wire [Y_WIDTH+2:0] C = {COx, CI}; wire dummy; - (* keep *) AL_MAP_ADDER #( .ALUTYPE("ADD_CARRY")) adder_cin ( @@ -55,19 +54,6 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) - AL_MAP_ADDER #( - .ALUTYPE("ADD")) - adder_cout ( - .c(C[Y_WIDTH]), - .o(COx[Y_WIDTH]) - ); - assign CO = COx[Y_WIDTH]; - end - else - begin - (* keep *) AL_MAP_ADDER #( .ALUTYPE("ADD") ) adder_i ( @@ -76,9 +62,15 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); .c(C[i+1]), .o({COx[i+1],Y[i]}) ); - end end: slice endgenerate /* End implementation */ + AL_MAP_ADDER #( + .ALUTYPE("ADD")) + adder_cout ( + .c(C[Y_WIDTH+1]), + .o(COx[Y_WIDTH+1]) + ); + assign CO = COx[Y_WIDTH+1]; assign X = AA ^ BB; endmodule
\ No newline at end of file |