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| author | Jannis Harder <me@jix.one> | 2023-02-13 12:26:06 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-13 12:26:06 +0100 |
| commit | 1698202ccc2f62d581673fd1320c3ab137f0261a (patch) | |
| tree | cebe60936fec53b518f37178e0b7e8df3c7ab7eb /techlibs/anlogic/brams_map.v | |
| parent | f3c4e93d2499dd96e331e49ad09540af9b9cd0bd (diff) | |
| download | yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.tar.gz yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.tar.bz2 yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.zip | |
sim: For yw cosim, drive parent module's signals for input ports
Diffstat (limited to 'techlibs/anlogic/brams_map.v')
0 files changed, 0 insertions, 0 deletions