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| author | Catherine <whitequark@whitequark.org> | 2021-12-15 08:15:54 +0000 |
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| committer | Catherine <whitequark@whitequark.org> | 2021-12-15 08:17:02 +0000 |
| commit | 4f1d62d9b25208f23a08b21247d016c44df01c26 (patch) | |
| tree | 7b3f1f59da020fb83dd7a49bfdb0f779912583e9 /techlibs/anlogic/brams_map.v | |
| parent | 48ed6d998bb2943891acd730c4aaef5d1deecb7e (diff) | |
| download | yosys-4f1d62d9b25208f23a08b21247d016c44df01c26.tar.gz yosys-4f1d62d9b25208f23a08b21247d016c44df01c26.tar.bz2 yosys-4f1d62d9b25208f23a08b21247d016c44df01c26.zip | |
bugpoint: avoid infinite loop between -connections and -wires.
Fixes #3113.
Diffstat (limited to 'techlibs/anlogic/brams_map.v')
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