diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 16:28:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-02 16:28:18 +0100 |
| commit | 56ca1e6afc66542666e73356cbe62f6ca64215a7 (patch) | |
| tree | ef73ada0584e9f8c0656e91fe6c16507600632dd /techlibs/anlogic/drams_map.v | |
| parent | b236faffa1f4e80f8af191469c89f582d3e0c324 (diff) | |
| parent | 90d00182cfe358438d777f2ca7abacb4c6a2733c (diff) | |
| download | yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.tar.gz yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.tar.bz2 yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.zip | |
Merge pull request #755 from Icenowy/anlogic-dram-init
anlogic: implement DRAM initialization
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v index 87cbb6a45..084e2a25f 100644 --- a/techlibs/anlogic/drams_map.v +++ b/techlibs/anlogic/drams_map.v @@ -1,4 +1,5 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; input CLK1; input [3:0] A1ADDR; @@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [3:0] B1DATA; input B1EN; - EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ ( + EG_LOGIC_DRAM16X4 #( + `include "dram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( .di(B1DATA), .waddr(B1ADDR), .wclk(CLK1), |