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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-17 17:16:10 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-17 17:16:10 +0100 |
| commit | 847fd360773d72933f1c728dba0755e0033350a6 (patch) | |
| tree | 0366fa1ca596e67aa583b540eb3b2e910bcc4c04 /techlibs/anlogic/drams_map.v | |
| parent | 3b4290a1b822aca42ceab4a89043329cb060325d (diff) | |
| parent | d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 (diff) | |
| download | yosys-847fd360773d72933f1c728dba0755e0033350a6.tar.gz yosys-847fd360773d72933f1c728dba0755e0033350a6.tar.bz2 yosys-847fd360773d72933f1c728dba0755e0033350a6.zip | |
Merge pull request #746 from Icenowy/anlogic-dram
Support for DRAM inferring on Anlogic FPGAs
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v new file mode 100644 index 000000000..87cbb6a45 --- /dev/null +++ b/techlibs/anlogic/drams_map.v @@ -0,0 +1,19 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |