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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
| commit | f443695a38fbdd8c2ca38cab45ca964a173dc158 (patch) | |
| tree | 4ac13e4fe8ee5e71f963c4230f9f26f32901c2ba /techlibs/anlogic/lutrams_map.v | |
| parent | d730bba6d2847515795c32d3a753320b8b48bee0 (diff) | |
| parent | da6abc014987ef562a577dc374bcb03aad9256cd (diff) | |
| download | yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.gz yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.bz2 yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.zip | |
Merge remote-tracking branch 'origin/master' into eddie/verific_help
Diffstat (limited to 'techlibs/anlogic/lutrams_map.v')
| -rw-r--r-- | techlibs/anlogic/lutrams_map.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/anlogic/lutrams_map.v b/techlibs/anlogic/lutrams_map.v new file mode 100644 index 000000000..5a464cafc --- /dev/null +++ b/techlibs/anlogic/lutrams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "lutram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |