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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
commit | 020606f81c39df234d7a3f5e3e605e5f27422d87 (patch) | |
tree | 8334168ea6ad76983226fa3bbc631ff151d4fedd /techlibs/anlogic/synth_anlogic.cc | |
parent | 36d79c80d05f93cd4cb565fe7a92d7cb88683852 (diff) | |
parent | b5f60e055d07579a2d4f23fc053ca030f103f377 (diff) | |
download | yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.gz yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.bz2 yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.zip |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
-rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index b87fc8566..aaa6bda4a 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -58,7 +58,10 @@ struct SynthAnlogicPass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); + log("\n"); + log(" -nolutram\n"); + log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nolutram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nolutram = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } if (args[argidx] == "-retime") { retime = true; continue; @@ -150,21 +158,25 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } - if (check_label("dram")) + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/anlogic/drams.txt"); - run("techmap -map +/anlogic/drams_map.v"); + run("memory_bram -rules +/anlogic/lutrams.txt"); + run("techmap -map +/anlogic/lutrams_map.v"); run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) @@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass run("techmap -map +/anlogic/cells_map.v"); run("clean"); } - + if (check_label("map_anlogic")) { run("anlogic_fixcarry"); |