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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
| commit | 295c18bd6b8d3fa503041904f7f7df392a4b5167 (patch) | |
| tree | 9a20c23d61a5c714ca8408c40d2e71345deff088 /techlibs/anlogic/synth_anlogic.cc | |
| parent | 4cc74346f11e96b9a2bce1c984c674a22771a00a (diff) | |
| parent | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (diff) | |
| download | yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.gz yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.bz2 yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..b87fc8566 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); - run("anlogic_determine_init"); + run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } if (check_label("fine")) @@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass { run("techmap -map +/anlogic/cells_map.v"); run("clean"); + } + + if (check_label("map_anlogic")) + { + run("anlogic_fixcarry"); run("anlogic_eqn"); } |