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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 15:53:50 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-02 15:53:50 +0100 |
| commit | b236faffa1f4e80f8af191469c89f582d3e0c324 (patch) | |
| tree | 83ab4e1230897004d9253028c98572cf4e56e22c /techlibs/anlogic/synth_anlogic.cc | |
| parent | 1eb101a38a0e6ca99cb1dfbcc77f16a6bff79465 (diff) | |
| parent | 979de95cf6a21aaa6f33cc3b20582333de6cf07d (diff) | |
| download | yosys-b236faffa1f4e80f8af191469c89f582d3e0c324.tar.gz yosys-b236faffa1f4e80f8af191469c89f582d3e0c324.tar.bz2 yosys-b236faffa1f4e80f8af191469c89f582d3e0c324.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 68f4399d4..fab199fd7 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -170,6 +170,7 @@ struct SynthAnlogicPass : public ScriptPass { run("dffsr2dff"); run("techmap -D NO_LUT -map +/anlogic/cells_map.v"); + run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit"); run("opt_expr -mux_undef"); run("simplemap"); } |