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author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
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committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /techlibs/anlogic/synth_anlogic.cc | |
parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
-rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 791dc922f..d7475df86 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -30,7 +30,7 @@ struct SynthAnlogicPass : public ScriptPass { SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -72,7 +72,7 @@ struct SynthAnlogicPass : public ScriptPass string top_opt, edif_file, json_file; bool flatten, retime, nolutram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file = ""; @@ -82,7 +82,7 @@ struct SynthAnlogicPass : public ScriptPass nolutram = false; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -137,7 +137,7 @@ struct SynthAnlogicPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { |