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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 16:44:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 16:44:18 -0800 |
| commit | 237415e78cab2c15d783657c4c2bc959efb298bb (patch) | |
| tree | 54fb66bd3ed9d644691635cd480ac01ad53e32e7 /techlibs/anlogic | |
| parent | a56d6970f24ae6044e02bea333c484035fd5cdfa (diff) | |
| download | yosys-237415e78cab2c15d783657c4c2bc959efb298bb.tar.gz yosys-237415e78cab2c15d783657c4c2bc959efb298bb.tar.bz2 yosys-237415e78cab2c15d783657c4c2bc959efb298bb.zip | |
write_xaiger: inherit port ordering from original module
Diffstat (limited to 'techlibs/anlogic')
0 files changed, 0 insertions, 0 deletions