Harmonize BRAM/LUTRAM descriptions across all of Yosys.

This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates

5 files changed, 22 insertions, 10 deletions

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 9426b5ca5..2d8d65e2e 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/lutram_init_16x4.vh
index 32fb1578c..32fb1578c 100644
--- a/techlibs/anlogic/dram_init_16x4.vh
+++ b/techlibs/anlogic/lutram_init_16x4.vh
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/lutrams.txt
index 4e903c0a2..4e903c0a2 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/lutrams.txt
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/lutrams_map.v
index 084e2a25f..5a464cafc 100644
--- a/techlibs/anlogic/drams_map.v
+++ b/techlibs/anlogic/lutrams_map.v
@@ -10,7 +10,7 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	input B1EN;
 
 	EG_LOGIC_DRAM16X4 #(
-		`include "dram_init_16x4.vh"
+		`include "lutram_init_16x4.vh"
 	) _TECHMAP_REPLACE_ (
 		.di(B1DATA),
 		.waddr(B1ADDR),
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index b87fc8566..3a1992588 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -60,6 +60,9 @@ struct SynthAnlogicPass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
+		log("    -nolutram\n");
+		log("        do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass
 	}
 
 	string top_opt, edif_file, json_file;
-	bool flatten, retime;
+	bool flatten, retime, nolutram;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass
 		json_file = "";
 		flatten = true;
 		retime = false;
+		nolutram = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass
 				flatten = false;
 				continue;
 			}
+			if (args[argidx] == "-nolutram") {
+				nolutram = true;
+				continue;
+			}
 			if (args[argidx] == "-retime") {
 				retime = true;
 				continue;
@@ -150,18 +158,22 @@ struct SynthAnlogicPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (check_label("dram"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/anlogic/drams.txt");
-			run("techmap -map +/anlogic/drams_map.v");
+			run("memory_bram -rules +/anlogic/lutrams.txt");
+			run("techmap -map +/anlogic/lutrams_map.v");
 			run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
 			if (retime || help_mode)
 				run("abc -dff", "(only if -retime)");
@@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass
 			run("techmap -map +/anlogic/cells_map.v");
 			run("clean");
 		}
-		
+
 		if (check_label("map_anlogic"))
 		{
 			run("anlogic_fixcarry");