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| author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
| commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
| tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /techlibs/anlogic | |
| parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
| download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip | |
Use C++11 final/override keywords.
Diffstat (limited to 'techlibs/anlogic')
| -rw-r--r-- | techlibs/anlogic/anlogic_eqn.cc | 4 | ||||
| -rw-r--r-- | techlibs/anlogic/anlogic_fixcarry.cc | 4 | ||||
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 8 |
3 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index e4fa4413f..e5fbc186f 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AnlogicEqnPass : public Pass { AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" anlogic_eqn [selection]\n"); @@ -63,7 +63,7 @@ struct AnlogicEqnPass : public Pass { return Const(eqn); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n"); diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index f8e70260c..c7dfe3c05 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -98,7 +98,7 @@ static void fix_carry_chain(Module *module) struct AnlogicCarryFixPass : public Pass { AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -107,7 +107,7 @@ struct AnlogicCarryFixPass : public Pass { log("Add Anlogic adders to fix carry chain if needed.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n"); diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 791dc922f..d7475df86 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -30,7 +30,7 @@ struct SynthAnlogicPass : public ScriptPass { SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -72,7 +72,7 @@ struct SynthAnlogicPass : public ScriptPass string top_opt, edif_file, json_file; bool flatten, retime, nolutram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file = ""; @@ -82,7 +82,7 @@ struct SynthAnlogicPass : public ScriptPass nolutram = false; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -137,7 +137,7 @@ struct SynthAnlogicPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { |