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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
| commit | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (patch) | |
| tree | ea54f3510f2e85771422718385028b0864696cba /techlibs/anlogic | |
| parent | 8ddec5d882c6834cb6b3415e05a2a88d416cabff (diff) | |
| parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
| download | yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.gz yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.bz2 yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Diffstat (limited to 'techlibs/anlogic')
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index 60a367928..058e76605 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -17,7 +17,7 @@ module AL_MAP_LUT1 ( ); parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign Y = INIT >> A; + assign o = INIT >> a; endmodule module AL_MAP_LUT2 ( |