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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-18 08:06:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-18 08:06:50 -0700 |
| commit | 2d573a0ff680eb9f38358943fbf134f765ba1451 (patch) | |
| tree | f68589c127fcb0972636699b888252972ed63385 /techlibs/common/Makefile.inc | |
| parent | fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa (diff) | |
| parent | 67fc0c3698693f049e805211c49d6219f17d7c7d (diff) | |
| download | yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.tar.gz yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.tar.bz2 yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.zip | |
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
Diffstat (limited to 'techlibs/common/Makefile.inc')
| -rw-r--r-- | techlibs/common/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 7b1e4b430..607e772a2 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -30,4 +30,6 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_map.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) |