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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 20:44:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 20:44:00 +0100 |
| commit | 1afe6589df136375c4322c9f10812e3b57f1200e (patch) | |
| tree | 64f7a5a2b49bd5bbf03504f67e136a594bd33a5a /techlibs/common/blackbox.sed | |
| parent | 8dafecd34d772b1d9ec190b39913b236cdc8fb17 (diff) | |
| download | yosys-1afe6589df136375c4322c9f10812e3b57f1200e.tar.gz yosys-1afe6589df136375c4322c9f10812e3b57f1200e.tar.bz2 yosys-1afe6589df136375c4322c9f10812e3b57f1200e.zip | |
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Diffstat (limited to 'techlibs/common/blackbox.sed')
| -rw-r--r-- | techlibs/common/blackbox.sed | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/blackbox.sed b/techlibs/common/blackbox.sed index 4e9a3a7c6..21693ecdd 100644 --- a/techlibs/common/blackbox.sed +++ b/techlibs/common/blackbox.sed @@ -1,4 +1,4 @@ #!/bin/sed -r -/^(wire|assign|reg)/ d; -/^(genvar|always|initial)/,/^end/ d; +/^(wire|assign|reg|event)/ d; +/^(genvar|generate|always|initial)/,/^end/ d; s/ reg / /; |