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author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
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committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /techlibs/common/cmp2lut.v | |
parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'techlibs/common/cmp2lut.v')
-rw-r--r-- | techlibs/common/cmp2lut.v | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v index ec8f98e8d..c753bd2f1 100644 --- a/techlibs/common/cmp2lut.v +++ b/techlibs/common/cmp2lut.v @@ -66,14 +66,12 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut; endfunction generate - if (_TECHMAP_CELLTYPE_ == "$lt") - localparam operation = 0; - if (_TECHMAP_CELLTYPE_ == "$le") - localparam operation = 1; - if (_TECHMAP_CELLTYPE_ == "$gt") - localparam operation = 2; - if (_TECHMAP_CELLTYPE_ == "$ge") - localparam operation = 3; + localparam operation = + _TECHMAP_CELLTYPE_ == "$lt" ? 0 : + _TECHMAP_CELLTYPE_ == "$le" ? 1 : + _TECHMAP_CELLTYPE_ == "$gt" ? 2 : + _TECHMAP_CELLTYPE_ == "$ge" ? 3 : + -1; if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1) wire _TECHMAP_FAIL_ = 1; |