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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:37:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:37:35 -0700 |
| commit | 2339b7fc3732996a217f635d95f1f7400cf43d48 (patch) | |
| tree | 744ed3df2d8db741a291a9e3c1f03f6f421f342c /techlibs/common/mul2dsp.v | |
| parent | 802470746c320676d61431d420e33d34c239da84 (diff) | |
| download | yosys-2339b7fc3732996a217f635d95f1f7400cf43d48.tar.gz yosys-2339b7fc3732996a217f635d95f1f7400cf43d48.tar.bz2 yosys-2339b7fc3732996a217f635d95f1f7400cf43d48.zip | |
mul2dsp to create cells that can be interchanged with $mul
Diffstat (limited to 'techlibs/common/mul2dsp.v')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..391b395ff 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -214,7 +214,13 @@ module \$__mul_gen (A, B, Y); else
wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
- `DSP_NAME _TECHMAP_REPLACE_ (
+ `DSP_NAME #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(`DSP_A_MAXWIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH),
+ .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH),
+ ) _TECHMAP_REPLACE_ (
.A(Aext),
.B(Bext),
.Y(Y)
|