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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
| commit | 24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch) | |
| tree | 131c64cee5a0cf09adc68b32f25e06a9da668ad0 /techlibs/common/simcells.v | |
| parent | 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff) | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.gz yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.bz2 yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.zip | |
Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 289673e82..64720e598 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -230,6 +230,25 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- +//- $_NMUX_ (A, B, S, Y) +//- +//- A 2-input inverting MUX gate. +//- +//- Truth table: A B S | Y +//- -------+--- +//- 0 - 0 | 1 +//- 1 - 0 | 0 +//- - 0 1 | 1 +//- - 1 1 | 0 +//- +module \$_NMUX_ (A, B, S, Y); +input A, B, S; +output Y; +assign Y = S ? !B : !A; +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- //- $_MUX4_ (A, B, C, D, S, T, Y) //- //- A 4-input MUX gate. |