diff options
| author | whitequark <whitequark@whitequark.org> | 2019-08-08 05:28:01 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-08-08 05:32:35 +0000 |
| commit | 0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8 (patch) | |
| tree | adef6cc5dea44944c6291b8fad222607ed68e7f9 /techlibs/common/simlib.v | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| download | yosys-0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8.tar.gz yosys-0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8.tar.bz2 yosys-0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8.zip | |
proc_prune: fix handling of exactly identical assigns.
Before this commit, in a process like:
process $proc$bug.v:8$3
assign $foo \bar
switch \sel
case 1'1
assign $foo 1'1
assign $foo 1'1
case
assign $foo 1'0
end
end
both of the "assign $foo 1'1" would incorrectly be removed.
Fixes #1243.
Diffstat (limited to 'techlibs/common/simlib.v')
0 files changed, 0 insertions, 0 deletions