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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-23 19:37:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-23 19:37:00 +0100 |
| commit | 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 (patch) | |
| tree | 30ec1719eadc3d0a991e0b94e54a3c1a623c66d9 /techlibs/common/simlib.v | |
| parent | 2521ed305e9d48929c9ede93b8cb0069739408f5 (diff) | |
| parent | b13e6bd375dc19fc2d6a3e67cdc6c045da732200 (diff) | |
| download | yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.tar.gz yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.tar.bz2 yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.zip | |
Merge branch 'forall'
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 276503fe8..8e43fe058 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1370,6 +1370,30 @@ endmodule // -------------------------------------------------------- +module \$allconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + +module \$allseq (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; |