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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 11:39:24 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 11:39:24 -0700 |
| commit | 1d14cec7fd41710aba0bb910a82fa5ca81c4adb0 (patch) | |
| tree | 32d7bf7782ec60cb4a61acba291ab3d4238df76f /techlibs/common/simlib.v | |
| parent | 9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a (diff) | |
| download | yosys-1d14cec7fd41710aba0bb910a82fa5ca81c4adb0.tar.gz yosys-1d14cec7fd41710aba0bb910a82fa5ca81c4adb0.tar.bz2 yosys-1d14cec7fd41710aba0bb910a82fa5ca81c4adb0.zip | |
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
Diffstat (limited to 'techlibs/common/simlib.v')
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