Merge branch 'master' of https://github.com/cliffordwolf/yosys

1 files changed, 22 insertions, 0 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 034244ca6..f3d652f0e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -55,6 +55,28 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$bu0 (A, Y);
+
+parameter A_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+`INPUT_A
+output [Y_WIDTH-1:0] Y;
+
+generate
+	if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+		assign Y[A_WIDTH-1:0] = A_BUF.val;
+		assign Y[Y_WIDTH-1:A_WIDTH] = 0;
+	end else begin:B
+		assign Y = +A_BUF.val;
+	end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$pos (A, Y);
 
 parameter A_SIGNED = 0;