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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-17 11:53:49 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 305672170bcd6346bebbb01c843225fe0392a37d (patch) | |
| tree | 069825d0093117bf650ae2401377f378452e8f21 /techlibs/common/simlib.v | |
| parent | bb70eb977dc29dbfe8cfb9af847046f387bd54b2 (diff) | |
| download | yosys-305672170bcd6346bebbb01c843225fe0392a37d.tar.gz yosys-305672170bcd6346bebbb01c843225fe0392a37d.tar.bz2 yosys-305672170bcd6346bebbb01c843225fe0392a37d.zip | |
adffs test update (equiv_opt -multiclock)
Diffstat (limited to 'techlibs/common/simlib.v')
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