Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig

1 files changed, 12 insertions, 6 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..9b6008140 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,10 +1464,11 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1483,10 +1484,11 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1504,10 +1506,11 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 wire pos_clk = CLK == CLK_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@@ -1537,10 +1540,11 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 wire pos_arst = ARST == ARST_POLARITY;
 
@@ -1559,10 +1563,11 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 always @* begin
 	if (EN == EN_POLARITY)
@@ -1580,10 +1585,11 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 wire pos_en = EN == EN_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;