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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-07 17:44:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-07 17:44:57 +0100 |
| commit | fc3b3c4ec3955b165166d9f44965fac0e1879505 (patch) | |
| tree | 2552ece4d6e1709f7ef17d838b00f7f774faf95b /techlibs/common/stdcells.v | |
| parent | a1ac710ab8740ae781e0274f63633e8ed2650da4 (diff) | |
| download | yosys-fc3b3c4ec3955b165166d9f44965fac0e1879505.tar.gz yosys-fc3b3c4ec3955b165166d9f44965fac0e1879505.tar.bz2 yosys-fc3b3c4ec3955b165166d9f44965fac0e1879505.zip | |
Added $slice and $concat cell types
Diffstat (limited to 'techlibs/common/stdcells.v')
| -rw-r--r-- | techlibs/common/stdcells.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v index e33e651ca..fdee26b6f 100644 --- a/techlibs/common/stdcells.v +++ b/techlibs/common/stdcells.v @@ -957,6 +957,18 @@ endmodule // -------------------------------------------------------- (* techmap_simplemap *) +module \$slice ; +endmodule + +// -------------------------------------------------------- + +(* techmap_simplemap *) +module \$concat ; +endmodule + +// -------------------------------------------------------- + +(* techmap_simplemap *) module \$mux ; endmodule |