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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 11:56:16 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 11:56:16 +0200 |
| commit | 5998c101a46c5121db0fa73b3af1f180a73d7fd5 (patch) | |
| tree | 8cfba156ab62fd7e61b1945cb1b6c6a983bcb0f0 /techlibs/common/stdcells_sim.v | |
| parent | 9bc703b9648c041f79f5a3460f93dfc6154a669b (diff) | |
| download | yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.tar.gz yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.tar.bz2 yosys-5998c101a46c5121db0fa73b3af1f180a73d7fd5.zip | |
Added $sr, $dffsr and $dlatch cell types
Diffstat (limited to 'techlibs/common/stdcells_sim.v')
0 files changed, 0 insertions, 0 deletions