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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-21 08:44:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-06-21 08:44:20 +0200 |
| commit | 7cddab0788cadc220ffa098c4ac037362ad6948e (patch) | |
| tree | 8df204605907e01759969afa2386274ea398c620 /techlibs/common/synth.cc | |
| parent | 541083cf329addb57117618de41697dd010d07cf (diff) | |
| parent | 545bcb37e8fa569d88374f92aafdcc1004e9b587 (diff) | |
| download | yosys-7cddab0788cadc220ffa098c4ac037362ad6948e.tar.gz yosys-7cddab0788cadc220ffa098c4ac037362ad6948e.tar.bz2 yosys-7cddab0788cadc220ffa098c4ac037362ad6948e.zip | |
Merge pull request #181 from rubund/input_logic_allowed
Allow defining input ports as "input logic" in SystemVerilog
Diffstat (limited to 'techlibs/common/synth.cc')
0 files changed, 0 insertions, 0 deletions