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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 15:14:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 15:14:31 -0700 |
| commit | 8f5710c464b2b3b91f0c7f29a9420dcb798be4c5 (patch) | |
| tree | 59bde082cba0f8f76e0e297ed57980592df7e73b /techlibs/common/synth.cc | |
| parent | f1a206ba03c5b6fba2672754d09cc649a60beeb8 (diff) | |
| parent | fd0e3a2c43d96ba31beede9865d5000230029994 (diff) | |
| download | yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.tar.gz yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.tar.bz2 yosys-8f5710c464b2b3b91f0c7f29a9420dcb798be4c5.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/common/synth.cc')
| -rw-r--r-- | techlibs/common/synth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); |