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| author | eshellko <kornukhin@mail.ru> | 2016-07-01 10:24:22 +0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-07-01 10:24:22 +0400 |
| commit | 9a742f4069d6413bcf46b84c3b3f0e5cfc47f647 (patch) | |
| tree | 2b7205866ff55746738d22fcf5ea0ae6434f03e9 /techlibs/common/synth.cc | |
| parent | df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86 (diff) | |
| download | yosys-9a742f4069d6413bcf46b84c3b3f0e5cfc47f647.tar.gz yosys-9a742f4069d6413bcf46b84c3b3f0e5cfc47f647.tar.bz2 yosys-9a742f4069d6413bcf46b84c3b3f0e5cfc47f647.zip | |
Added 'assert-limit' option for 'select' command
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
Diffstat (limited to 'techlibs/common/synth.cc')
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