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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-08-29 21:07:34 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-29 21:07:34 +0300 |
| commit | d360693040dda29aba4ef2583e522c6ab88a4961 (patch) | |
| tree | 3de073925c8e3a4a613303ea807aeef12949a3d7 /techlibs/common/synth.cc | |
| parent | d588c6898fb7cfebe52a71a48d6fb21d1623e61b (diff) | |
| parent | b8a9f73089234ed699a4057b50fd739a90abea43 (diff) | |
| download | yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.gz yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.bz2 yosys-d360693040dda29aba4ef2583e522c6ab88a4961.zip | |
Merge pull request #3 from YosysHQ/Sergey/tests_ice40
Merge my changes to tests_ice40 branch
Diffstat (limited to 'techlibs/common/synth.cc')
| -rw-r--r-- | techlibs/common/synth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); |