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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:59:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:59:05 +0200 |
| commit | 4724d94fbce587b39cd7343dc8de3b859311f55c (patch) | |
| tree | 6a1c2a9b82d48f73dbcaa3926003bbcf85b48a0f /techlibs/common/techmap.v | |
| parent | 88db09255baa92facbe2736937ef113dc1503e9b (diff) | |
| download | yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.tar.gz yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.tar.bz2 yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.zip | |
Added $alu cell type
Diffstat (limited to 'techlibs/common/techmap.v')
| -rw-r--r-- | techlibs/common/techmap.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 452b64b8f..d6b249456 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -359,7 +359,7 @@ module \$__alu_lookahead (A, B, CI, X, Y, CO); assign carry = {CO, CI}; endmodule -module \$__alu (A, B, CI, BI, X, Y, CO); +module \$alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -370,7 +370,6 @@ module \$__alu (A, B, CI, BI, X, Y, CO); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] X, Y; - // carry in, sub, carry out, carry sign input CI, BI; output [Y_WIDTH-1:0] CO; @@ -410,7 +409,7 @@ endmodule wire [WIDTH-1:0] alu_x, alu_y, alu_co; wire [WIDTH:0] carry = {alu_co, |_sub}; - \$__alu #( + \$alu #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), |