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| author | Jannis Harder <me@jix.one> | 2022-11-02 17:12:51 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 (patch) | |
| tree | da57415b2168bf02cb0efa485a91769850e66cf8 /techlibs/common/techmap.v | |
| parent | f2c531e65f4518abe58d04e53d0116583651ac50 (diff) | |
| download | yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.tar.gz yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.tar.bz2 yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.zip | |
Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
Diffstat (limited to 'techlibs/common/techmap.v')
| -rw-r--r-- | techlibs/common/techmap.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 91d385b80..7fb8173b0 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -59,7 +59,7 @@ module _90_simplemap_compare_ops; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *) +(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) module _90_simplemap_various; endmodule |