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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-24 16:02:29 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-28 23:34:41 +0100 |
commit | 93508d58dafbbffcedffa70b21a197b6fca8bb30 (patch) | |
tree | 4f4bed22749559a1938457015ff875891fd7a40a /techlibs/common/techmap.v | |
parent | db33b1e535f5ee93dba9ee1cc181b91c482a4dee (diff) | |
download | yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.gz yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.bz2 yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.zip |
Add $bmux and $demux cells.
Diffstat (limited to 'techlibs/common/techmap.v')
-rw-r--r-- | techlibs/common/techmap.v | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 667773e1b..91d385b80 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -59,7 +59,7 @@ module _90_simplemap_compare_ops; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$pos $slice $concat $mux $tribuf" *) +(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *) module _90_simplemap_various; endmodule @@ -597,6 +597,43 @@ module _90_pmux (A, B, S, Y); assign Y = |S ? Y_B : A; endmodule +// -------------------------------------------------------- +// Demultiplexers +// -------------------------------------------------------- + +(* techmap_celltype = "$demux" *) +module _90_demux (A, S, Y); + parameter WIDTH = 1; + parameter S_WIDTH = 1; + + (* force_downto *) + input [WIDTH-1:0] A; + (* force_downto *) + input [S_WIDTH-1:0] S; + (* force_downto *) + output [(WIDTH << S_WIDTH)-1:0] Y; + + generate + if (S_WIDTH == 0) begin + assign Y = A; + end else if (S_WIDTH == 1) begin + assign Y[0+:WIDTH] = S ? 0 : A; + assign Y[WIDTH+:WIDTH] = S ? A : 0; + end else begin + localparam SPLIT = S_WIDTH / 2; + wire [(1 << (S_WIDTH-SPLIT))-1:0] YH; + wire [(1 << SPLIT)-1:0] YL; + $demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL)); + $demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH)); + genvar i; + for (i = 0; i < (1 << S_WIDTH); i = i + 1) begin + localparam [S_WIDTH-1:0] IDX = i; + assign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0; + end + end + endgenerate +endmodule + // -------------------------------------------------------- // LUTs |