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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
| commit | 21e1bac0846e01fb58ae1fd42215b92f245ae18d (patch) | |
| tree | 43c1c9fff3a78d7221c6e5dfbfebe820b311afa1 /techlibs/common | |
| parent | 5fe13a16eaaee4ac53523b5325cb9d92b5a1150d (diff) | |
| parent | da56a5bbc60e58c305227105b68654264738c241 (diff) | |
| download | yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.gz yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.bz2 yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 8ab124034..ac4269c90 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1330,6 +1330,30 @@ endmodule // -------------------------------------------------------- +module \$aconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + +module \$anyconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; |