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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 14:45:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 14:45:47 -0700 |
| commit | 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 (patch) | |
| tree | 461fcbeb36e8ab620f391817270497e6f22e8053 /techlibs/common | |
| parent | 0c7ee6d0fa14b634ffbde5ad79983cb89372a697 (diff) | |
| download | yosys-42f8e68e76a3717cf4ad29c36f0a9a801cde52c1.tar.gz yosys-42f8e68e76a3717cf4ad29c36f0a9a801cde52c1.tar.bz2 yosys-42f8e68e76a3717cf4ad29c36f0a9a801cde52c1.zip | |
OUT port to Y in generic DSP
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..0a87716d9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -209,7 +209,7 @@ module \$__mul_gen (A, B, Y); `DSP_NAME _TECHMAP_REPLACE_ (
.A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),
.B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),
- .OUT({dummy, out})
+ .Y({dummy, out})
);
if (Y_WIDTH < A_WIDTH+B_WIDTH)
assign Y = out[Y_WIDTH-1:0];
|